2021 计算机组成与设计：RISC-V(浙江大学) 最新满分章节测试答案

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本课程起止时间为:2021-09-16到2021-12-31
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第三章、RISC-V指令表示 经典论文课后阅读自测

1、 问题:What are the techniques to keep integrated structures small in size?
选项：
A:By applying thin-film structures
B:By ultilizing semiconductor-based integrated circuits rather than the out-dated vacumn tubes
C:By placing transistors within their own silicon wafer and connecting them efficiently
D:By leveraging microassembly techniques to organize individual components
答案: 【By applying thin-film structures;
By ultilizing semiconductor-based integrated circuits rather than the out-dated vacumn tubes;
By leveraging microassembly techniques to organize individual components】

2、 问题:What are the key factors that contribute to the popularity of integrated circuits?
选项：
A:reliability
B:performance
C:cost
D:weight
答案: 【reliability;
performance;
cost】

3、 问题:Choose all the false statement(s) below concerning Moore’s Law.
选项：
A:Moore’s Law describes the rule of what the IC manufacture and design follows starting from the very beginning of IC invention towards the future.
B:There exists a strong incentive to increase the device yield of ordinary ICs today in order to keep pace with Moore’s Law.
C:Moore initially expected that the complexity could double every year, which was eventually quoted as the famous Moore’s Law.
D:q
答案: 【Moore’s Law describes the rule of what the IC manufacture and design follows starting from the very beginning of IC invention towards the future.;
There exists a strong incentive to increase the device yield of ordinary ICs today in order to keep pace with Moore’s Law.;
Moore initially expected that the complexity could double every year, which was eventually quoted as the famous Moore’s Law.】

4、 问题:Choose all the false statement(s) below concerning Moore’s Law.
选项：
A:Moore’s Law describes the rule of what the IC manufacture and design follows starting from the very beginning of IC invention towards the future.
B:There exists a strong incentive to increase the device yield of ordinary ICs today in order to keep pace with Moore’s Law.
C:Moore initially expected that the complexity could double every year, which was eventually quoted as the famous Moore’s Law.
D:-
答案: 【Moore’s Law describes the rule of what the IC manufacture and design follows starting from the very beginning of IC invention towards the future.;
There exists a strong incentive to increase the device yield of ordinary ICs today in order to keep pace with Moore’s Law.;
Moore initially expected that the complexity could double every year, which was eventually quoted as the famous Moore’s Law.】

5、 问题:Memory could be organized inside the machine in a distributed manner rather than just being centralized. True or false?
选项：
A:正确
B:错误
答案: 【正确】

6、 问题:Shrinking dimensions over an integrated structure does not make sense due to the heat problem even if the power consumption remains the same. True or false?
选项：
A:正确
B:错误
答案: 【错误】

第四章、RISC-V数据通路 第四章单元测验

1、 问题:From the perspective of the CPU hardware model, which of the following are definitely not the basic components of the CPU?
选项：
A:ALU
B:Main memory
C:Cache
D:Controller
答案: 【Main memory】

2、 问题:Single-cycle RISC-V datapath cannot complete which of the following operations in one clock cycle.
选项：
A:Reading data from and writing data to data memory
B:ALU computation and writing data to the register file
C:Updating PC and writing data to data memory
D:Reading data from register file, ALU computation and writing data to data memory
答案: 【Reading data from and writing data to data memory】

3、 问题:The bit width of PC is determined by (   ).
选项：
A:Memory word length
B:Memory capacity
C:Instruction word length
D:Bit width of general-purpose registers
答案: 【Memory capacity】

4、 问题:Problem in this exercise assume that the logic blocks used to implement a processor’s complete datapath have the following latencies:“Register read” is the time needed after the rising clock edge for the new register value to appear on the output. This value applies to the PC only. “Register setup” is the amount of time a register’s data input must be stable before the rising edge of the clock. This value applies to both the PC and Register File.Q1: What is the latency of an R-type instruction?____ ps ( number only )
答案: 【700】

5、 问题:For conditions in question 4.Q2: What is the latency of lw instruction?____ ps (number only )
答案: 【950】

6、 问题:For conditions in question 4.Q3: What is the latency of sw instruction?____ ps ( number only )
答案: 【905】

7、 问题:For conditions in question 4.Q4: What is the latency of beq instruction?____ ps ( number only )
答案: 【705】

8、 问题:For conditions in question 4.Q5: What is the latency of I-type instruction?____ ps ( number only )
答案: 【700】

9、 问题:For conditions in question 4.Q6: What is the minimum clock period for this CPU?____ ps ( number only )
答案: 【950】

第五章、RISC-V控制器 第五章单元测验

1、 问题:For the following single-cycle datapath, answer the questions:Q1: When execute sub instruction, the control signals PCSel, ASel, BSel, RegWEn, and WBSel generated by the controller are respectively (     ).
选项：
A:0, 1, 0, 1, 1
B:0, 0, 0, 1, 0
C:0, 0, 1, 1, 1
D:0, 0, 0, 1, 1
答案: 【0, 0, 0, 1, 1】

2、 问题:For conditions in question 7.Q2: When execute lw instruction, the control signals PCSel, ASel, BSel, RegWEn, and WBSel generated by the controller are respectively (     ).
选项：
A:0, 0, 0, 1, 1
B:0, 0, 1, 1, 2
C:0, 1, 1, 1, 0
D:0, 0, 1, 1, 1
答案: 【0, 0, 1, 1, 2】

3、 问题:For conditions in question 7.Q2: When execute jalr instruction, the control signals PCSel, ImmSel, ASel, BSel, RegWEn, and WBSel generated by the controller are respectively (     ).
选项：
A:1, J, 0, 1, 1, 2
B:1, I, 0, 1, 0, 2
C:1, I, 0, 1, 1, 2
D:1, J, 0, 1, 1, 1
答案: 【1, I, 0, 1, 1, 2】

4、 问题:For the following single-cycle datapath, answer the questions:When silicon chips are fabricated, defects in materials and manufacturing errors can result in defective circuits. A very common defect is for one signal wire to get "broken" and always register a logical 0. This is often called a "stuck-at-0" fault.Q1: Which instructions fail to operate correctly if the ASel wire is stuck at 0?
选项：
A:B-Format
B:I-Format
C:J-Format
D:U-Format
答案: 【B-Format;
J-Format;
U-Format】

5、 问题:For conditions in question 1.Q2: Which instructions fail to operate correctly if the RegWEn wire is stuck at 0?
选项：
A:R-Format
B:I-Format
C:J-Format
D:U-Format
答案: 【R-Format;
I-Format;
J-Format;
U-Format】

6、 问题:For conditions in question 1.Q3: Which instructions fail to operate correctly if the WBSel wire is stuck at 0?
选项：
A:lw
B:jalr
C:beq
D:jal
答案: 【lw;
jalr;
jal】

7、 问题:Assume the delay for each stage in the single-cycle datapath is as follows:IFIDEXMEMWB200ps100ps200ps200ps100psQ1: The total time needed to execute ori instruction is _____ps.
答案: 【600】

8、 问题:For conditions in question 4.Q2: The total time needed to execute beq instruction is _____ps.
答案: 【500】

9、 问题:For conditions in question 4.Q3: The fastest frequency you could clock this single-cycle datapath is _____GHz.
答案: 【1.25】

第六章、流水线 第六章单元测验

1、 问题:For conditions in question 1.Q2: If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split to improve the performance of the processor?
选项：
A:IF
B:ID
C:EX
D:MEM
答案: 【ID】

2、 问题:For conditions in question 4.Q3: Say you are the compiler and can re-order instructions to minimize data hazards while guaranteeing the same output. How can you fix the code order above?
选项：
A:1-3-2-4
B:2-3-1-4
C:2-4-1-3
D:1-4-2-3
答案: 【2-3-1-4】

3、 问题:For conditions in question 7.Q2: There is a control hazard between instructions 4 and 5. (True or False)
选项：
A:正确
B:错误
答案: 【正确】

4、 问题:Assuming the individual stages of the datapath have the following latencies:IFIDEXMEMWB250ps350ps150ps300ps200psQ1: What is the clock cycle time in a pipelined processor? _____ps
答案: 【350】

5、 问题:For conditions in question 2.Q3: What is the new clock cycle time of the processor? _____ps
答案: 【300】

6、 问题:Given the RISC-V code below and a pipelined CPU with no forwarding.Q1: How many data hazard(s) in the codes above? _____(number only)
答案: 【2】

7、 问题:For conditions in question 4.Q2: How many data hazard(s) cannot be solved with forwarding? _____(number only)
答案: 【1】

8、 问题:Given the RISC-V code below and a pipelined CPU with no forwarding.Q1: How many data hazard(s) in the codes above? _____(number only)
答案: 【3】

9、 问题:For conditions in question 7.Q3: How many stalls would there need to be in order to fix all data hazard(s) (assuming that we can read and write to the RegFile on the same cycle)? _____(number only)
答案: 【4】

10、 问题:For conditions in question 7.Q4: How many stalls would there need to be in order to fix the control hazard(s) with branch prediction/flushing? _____(number only)
答案: 【0】

第七章、高速缓存结构 第七章单元测验